1. Field of the Invention
The present invention relates to a manufacturing method for a semiconductor device that is improved so that the negative effects of shadowing of a resist due to miniaturization can be prevented at the time of diagonal ion implantation.
2. Description of the Background Art
As miniaturization progresses, short channel effects, and the like, occurs in transistor characteristics so that the requirements for overcoming this become stringent. Short channel effects refers to the phenomenon wherein the threshold voltage falls as the gate length is shortened in reference to the curve shown by the solid line in FIG. 7. When the threshold voltage falls it becomes difficult to control the transistor and, therefore, it becomes necessary to raise the threshold voltage according to the curve shown by the dotted line in the figure. As a technology for achieving this purpose, a drain engineering technology using a diagonal ion implantation such as the below described SPI (shallow pocket implant) structure, or the like, has increased in importance.
The technology using the diagonal ion implantation is also used for formation of an LDD (lightly doped drain) structure wherein an electrical field relaxation is carried out on a transistor. FIG. 8A shows an example wherein extension parts 30 of an LDD structure are formed using diagonal ion implantation technology.
FIG. 8B shows an example wherein a transistor of an SPI (shallow pocket implant) structure, or the like, is formed using diagonal ion implantation technology in order to suppress the above described short channel effect. The SPI structure is implemented by forming a punch through stopper layer 31 of the conductive type opposite to that of the source/drain regions beneath the source/drain regions.
In the present specification, drain engineering means to improve the structure of a drain of a transistor and, more concretely, is defined as adjusting the impurity profile in an LDD or in an SPI.
A technology that makes full use of diagonal ion implantation is widely utilized in drain engineering for transistors.
In a diagonal ion implantation technology, however, a (shadowing) region of no implantation occurs at a resist mask edge portion due to shadow formation. Accordingly, as miniaturization progresses this shadow region becomes an obstacle against miniaturization. In addition, the effects of this shadowing on the device become greater as miniaturization progresses to the extent that they can not be ignored.
This is described further in detail.
FIGS. 9 to 11 schematically show a layout of an actual LSI (Large Scale Integrated circuit) such as, for example, an inverter. Here, this is an example of a theoretically implemented case and such a structure can not be gained according to a prior art as described below.
FIG. 9 is a plan view and FIG. 10 is a cross sectional view along line Xxe2x80x94X in FIG. 9. FIG. 11 is a cross sectional view along line XIxe2x80x94XI in FIG. 9. FIG. 12 is an equivalent circuit diagram of this inverter circuit.
Referring to these figures, a P type well region 1 that forms an NMOSFET (N-channel Metal Oxide Semiconductor Field Effect Transistor) and an N type well region 2 that forms a PMOSFET (P-channel Metal Oxide Semiconductor Field Effect Transistor) are formed in the surface of a semiconductor substrate 60. A trench isolation region 8 is formed in the surface of semiconductor substrate 60. Source/drain regions 3 that are N type diffusion regions are formed in P type well region 1. A well contact region 4 that is a P type diffusion region is formed in P type well region 1 in order to make an electrical contact 32 with P type well region 1. A swelling portion 7a in the center portion of a gate electrode 7 is formed so as to become swollen in order to easily make an electrical contact. Source/drain regions 5 that are P type diffusion regions of a PMOS (P-channel Metal Oxide Semiconductor) transistor are formed in N type well region 2. Furthermore, an N type diffusion region 6 for making an electrical contact 33 with the N type well region is formed in N type well region 2. An N-diffusion layer 9 that is formed by using diagonal implantation is provided beneath gate electrode 7 and this forms extension parts of an LDD transistor.
FIGS. 13 to 15 are views showing the steps of forming, for example, N-diffusion layer 9 beneath the gate by using diagonal implantation in the above described structural layout. FIG. 13 is a plan view, FIG. 14 is a cross sectional view along line XIVxe2x80x94XIV in FIG. 13 and FIG. 15 is a cross sectional view along line XVxe2x80x94XV in FIG. 13. Here, FIG. 13 also illustrates source/drain regions 3 and 5 as well as well contact regions 4 and 6 in order to clarify the positional relationships.
Referring to these figures, regions into which ions are not implanted are covered with a resist 10. Arrow 20 schematically shows an incident path from a specific direction of a beam for implantation seeds that are diagonally implanted.
As shown in FIGS. 14 and 15, in the case that the distance between resist 10 and N type diffusion region 3 or a region indicated by reference number 6 (implantation may sometimes not be carried out, simultaneously, in the portion indicated by reference number 6) is insufficient, ions are implanted only in region 9 and a (shadowing) region of no implantation 9a occurs due to the shadow of resist 10, although this depends on the relationship between the incident angle of the beam and the height of resist 10. Such shadowing 9a depends on the distance between resist 10 and N type diffusion region 3 or the region indicated by reference number 6. Accordingly, in the case that there is dispersion of this distance, different transistors are formed according to a layout within the LSI and, as a result, the transistor characteristics become dispersed in the respective transistors.
It becomes increasingly difficult to sufficiently secure the above distance as miniaturization advances and the greater the miniaturization of the transistor, the greater the effect of shadowing becomes to the extent such that dispersion cannot be ignored.
In addition, the same problem of shadowing occurs in the case that an SPI is formed wherein the problem occurs that the short channel effects cannot be suppressed in the transistors of which the characteristics are dispersed.
This invention is provided in order to solve the above described problems and a manufacturing method for a semiconductor device that is improved so that the dispersion of the transistors can be prevented is provided.
Another purpose of this invention is to provide a manufacturing method for a semiconductor device that is improved such that the short channel effects can be suppressed regardless of dispersion due to shadowing.
In a manufacturing method for a semiconductor device according to claim 1, first, a well of a first conductive type is formed in a semiconductor substrate (first step). A gate electrode for forming a first transistor is formed on the above described well of the first conductive type (second step). A diagonal ion implantation for drain engineering is carried out in portions beneath the above described gate electrode and in a portion wherein a well contact region for making an electrical contact with the well of the first conductive type is formed in the main surface of the above described well of the first conductive type (third step). Source/drain regions of a second conductive type are formed in the main surface of the above described well of the first conductive type on both sides of the above described gate electrode (fourth step). Ions of the first conductive type are implanted into a portion in which the above described well contact region is formed so as to form a well contact region of the first conductive type (fifth step). The above described diagonal ion implantation in the above described third step and the above described ion implantation in the above described fourth step are carried out so that when the depth is plotted along the longitudinal axis and the impurity concentration is plotted along the lateral axis in the impurity profile of the above described well contact region, the impurity profile of the first conductive type that forms the above described well contact region covers the impurity profile that forms the above described impurity diffusion layer.